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|Product Name:||10G 1310nm SFP Transceiver||Distance:||10Km|
fiber sfp module,
optical amplifier module
10G 1310nm SFP Transceiver Module XYT-tech SFP LR 10km 20km Fiber Optic Module
10Gb/s 1310nm SFP+ 10km Transceiver
SFP+ -10G-1310nm-SM-10km-DDM transceivers support the 2-wire serial communication protocol as defined in the SFP+ MSA.
The standard SFP serial ID provides access to identification information that describes the transceiver’s capabilities, standard interfaces, manufacturer, and other information.
Additionally, SFP+ transceivers provide a unique enhanced digital diagnostic monitoring interface, which allows real-time access to device operating parameters such as transceiver temperature, laser bias current, transmitted optical power, received optical power and transceiver supply voltage. It also defines a sophisticated system of alarm and warning flags, which alerts end-users when particular operating parameters are outside of a factory set normal range.
The SFP MSA defines a 256-byte memory map in EEPROM that is accessible over a 2-wire serial interface at the 8 bit address 1010000X (A0h).The digital diagnostic monitoring interface makes use of the 8 bit address 1010001X (A2h), so the originally defined serial ID memory map remains unchanged.
The operating and diagnostics information is monitored and reported by a Digital Diagnostics Transceiver Controller (DDTC) inside the transceiver, which is accessed through a 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL, Mod Def 1) is generated by the host. The positive edge clocks data into the SFP transceiver into those segments of the E2PROM that are not write-protected. The negative edge clocks data from the SFP transceiver. The serial data signal (SDA, Mod Def 2) is bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories are organized as a series of 8-bit data words that can be addressed individually or sequentially.
|Input differential impedance||Rin||100||Ω||1|
|Single ended data input swing||Vin,pp||180||700||mV|
|Transmit Disable Voltage||VD||Vcc–1.3||Vcc||V|
|Transmit Enable Voltage||VEN||Vee||Vee+ 0.8||V||2|
|Transmit Disable Assert Time||10||us|
|Differential data output swing||Vout,pp||300||850||mV||3|
|Data output rise time||tr||28||ps||4|
|Data output fall time||tf||28||ps||4|
|LOS Fault||VLOS fault||Vcc–1.3||VccHOST||V||5|
|LOS Normal||VLOS norm||Vee||Vee+0.8||V||5|
|Power Supply Rejection||PSR||100||mVpp||6|
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